Field of the Invention
The present invention relates to a motor driving device for driving a motor.
Description of the Related Art
FIG. 8 is a diagram illustrating a configuration of an ordinary motor driving circuit 100. Four FETs Q1 to Q4 (hereinafter, referred to simply as Q1 to Q4) are connected to each other in a bridge configuration, and a coil L1 of a motor is connected so as to bridge the connection points of Q1 and Q3, and the connection points of Q2 and Q4. In FIGS. 8, Q1 to Q4 are n-channel FETs, and the drain terminals of Q1 and Q2 are connected to a terminal of a 24V-power supply. Furthermore, the source terminals of Q3 and Q4 are connected to the ground (GND). Furthermore, Q1 and Q4 are driven with the same PWM signal PWM+, and Q2 and Q3 are driven with the same PWM signal PWM−. Note that PWM+ and PWM− have a relationship in which their phases are opposite each other.
The following will describe an operation of the motor driving circuit 100 with reference to FIG. 9. Note that in FIG. 9, a time period T1 is a time period in which a phase current I flowing through the coil L1 of FIG. 8 is positive (in the direction of the arrow), and a time period T2 is a time period in which the phase current I is negative (in the direction opposite to the arrow). Note that the phase current is a driving current for driving a motor. During the time period T1 in which the phase current I is positive, when PWM+ is high, the phase current I flows as shown by the solid lines of FIG. 9. Then, when PWM+ is low, an induced electromotive voltage is generated in the coil Ll in a direction in which it prevents a change in the electric current. This induced electromotive voltage is predominant compared to the 24V of the power supply for driving a motor, and the phase current I flows as shown by the dotted lines of FIG. 9 (regenerative current). On the other hand, during the time period T2 in which the phase current I is negative, when PWM+ is low, the phase current I flows as shown by the solid lines of FIG. 9, and then when PWM+ is high, the phase current I flows, as shown in the dotted lines, due to the induced electromotive voltage generated in the coil L1.
In order to drive the motor driving circuit 100 appropriately, a control unit for controlling the motor needs to detect the phase current I. Points A, B, and C of FIG. 8 are points at which the phase current I may be detected. Here, if the electric current is to be detected at the points A and B, a current detection unit to which a high voltage of 24V can be input will need to be provided, resulting in an increase in the cost. On the other hand, if the electric current is to be detected at the point C, electric current detection will be possible using an inexpensive part. However, during the time period T1 in which the direction of the phase current I is positive, when PWM+ is high, an electric current flows from the power supply terminal toward GND via Ql, the coil L1, and Q4 in the stated order. On the other hand, during the time period T1 in which the direction of the phase current I is positive, when PWM+ is low, an electric current flows from GND toward the power supply terminal via Q3, the coil L1, and Q2 in the stated order. In other words, during the time period T1 in which the direction of the phase current I is positive, the electric currents flowing in two directions, namely, the direction toward GND and the direction from GND, both pass through the point C. The same applies to the time period in which the direction of the phase current I is negative. In other words, if a detection resistor is provided at the point C so as to obtain voltages Vsns at its two ends, only the waveform shown in FIG. 9 will be obtained, and the direction of the phase current cannot be determined.
Accordingly, U.S. Pat. No. 5,574,344 discloses a configuration in which, when a differential amplifier amplifies a voltage of a detection resistor provided at the point C, the polarity of the voltage of the detection resistor that is input to the differential amplifier is switched in synchronization with a PWM signal.
FIG. 10 is a timing chart of signals when the time period in which the PWM signal is high or low is very short. In FIG. 10, for example, during the time period T1 in which the phase current is positive, PWM+ is low only during a very short time period Toff1. In this very short time period Toff1, where PWM+ is low, Q1 and Q4 are ideally in the OFF state, but are actually kept in the ON state. This is because, during the time period Toff1, the gate charges of Q1 and Q4 are not sufficiently discharged, and thus the voltages between the gates and the sources do not become lower than a threshold voltage. Accordingly, as shown in FIG. 10, during the time period Toffl, the voltage Vsns remains positive, and as a result, an input to the differential amplifier of the configuration of U.S. Pat. No. 5,574,344 is negative as shown in FIG. 10. Accordingly, also the configuration of U.S. Pat. No. 5,574,344 cannot correctly detect the phase current I. Furthermore, there is a risk that the switching of the PWM signal between high and low will generate switching noise in Q1 to Q4, and the generated switching noise will overlap with the detected current value. Also in this case, it is not possible to correctly detect the phase current I.